A semiconductor digital memory such as a static random access memory (SRAM) is arranged as an array of individual memory cells, each cell storing a single bit of information, either a 1, high voltage, or a 0, low voltage.
The basic SRAM cell is well known. FIG. 1 illustrates a typical circuit schematic for an SRAM cell utilizing load resistors R.sub.1 and R.sub.2 connected to the V.sub.CC line. Alternatively, resistors R.sub.1 and R.sub.2 may each be replaced by a transistor having a selectively biased gate, forming the equivalent of a load resistor. Pull down transistors T.sub.1 and T.sub.2 are cross-coupled to ensure that when one of those transistors is off, the other transistor is on. For instance, if transistor T.sub.2 is on then the voltage on node A is low, approximately at ground, while transistor T.sub.1 is off and the voltage on node B is high, approximately at V.sub.CC. In this case the current through R.sub.2 is typically tens of pico-amps if R.sub.2 has a high resistance value such as 100 giga-ohms. Conversely, if transistor T.sub.1 is on then the voltage on node B is low while transistor T.sub.2 is off and the voltage at node A is high.
Pass transistors T.sub.3 and T.sub.4 act as switches to enable measurement for change in the state of the cell. Transistors T.sub.3 and T.sub.4 are turned on by the bit select control signal produced from the external decoding of address lines. For instance, if the voltage on node A is low, this state is detected at bit line BL when pass transistor T.sub.4 is turned on by applying a high level signal to the word line WL in a well-known manner. The state of the SRAM cell may be changed by forcing the appropriate bit line BL or BL to ground.
In the prior art each circuit line including both bit lines BL and BL, word line WL, the V.sub.CC line and the V.sub.SS line are typically formed from conductive layers above the silicon substrate.
FIGS. 2 and 3 show a group of four SRAM cells having a prior art cell layout. In FIGS. 2 and 3, which show only some of the cell components for clarity, each cell occupies one quadrant as divided along lines A--A and B--B. A legend for interpreting the different shading types and outlines is provided as FIG. 4.
Reference numerals 1 and 2 each indicate the gate of one pull down transistor of the cell occupying the lower right hand quadrant of FIG. 2. Mask lines 22a and 22b outline the mask openings which may be used to open gate contacts 3a and 3b, respectively, through an overlying oxide layer (not shown). Shaded areas 4a-4d show the location of active island regions which are separated by field oxide 5. Reference numbers 4a and 4b indicate drain regions and reference numbers 4c and 4d indicate source regions. Buried contacts 6a and 6b are each formed as openings in an insulating layer overlying the active regions for exposing the drain region of each pull down transistor of the cell.
A conductive strip forms cross-coupling interconnect 7a which electrically connects the drain region exposed by buried contact 6a to gate 2, exposed by gate contact 3b. Similarly, a second conductive strip forms cross-coupling interconnect 7b which electrically connects the drain region exposed by buried contact 6b to gate 1, exposed by gate contact 3a. In this way, the drain of each pull down transistor is electrically connected to the gate of the other pull down transistor in each cell and, thus, the two pull down transistors are cross-coupled.
Word line 8 is formed as a long conductive strip which extends across adjacent cells. Word line 8 also functions as the gate for the two pass transistors of each cell. The V.sub.SS line 9 which functions as a ground line is formed as a long conductive strip positioned to serve as the V.sub.SS line for adjacent SRAM cells on both sides in FIG. 2. In this example V.sub.SS line 9 is a composite of two materials. The first material is a doped region of the silicon substrate which is an extension of the source regions such as 4c and 4d of the pull down transistors. The second material is a layer of conductive material such as titanium silicide which covers and completely contacts the underlying doped region.
The V.sub.CC line 10 is formed as a conductive strip which is positioned above and orthogonal to gates 1 and 2 of the pull down transistors. V.sub.CC line 10 is insulated from the underlying cell components, typically by deposited silicon oxide.
Buried contacts 15a and 15b are formed as openings through an insulating layer to expose doped regions of the substrate between two word lines of adjacent cells, as can be inferred upon realizing that the four cell layout shown is repeated to form a memory array. Conductive portions 11a, 11b, which may be titanium silicide, completely cover each buried contact 15a, 15b. Although conductive portions 11a, 11b may overlap word line 8, they are insulated from it by the dielectric material which covers word line 8. Conductive portions 11a, 11b help connect the bit lines to the drains of the pass transistors of each cell as described below.
FIG. 3 adds load resistors, load resistor vias and metal bit lines to the layout of FIG. 2. Heavy solid line 26a outlines the load resistors. Mask opening lines 27a, 27b, and 27c outline load resistor vias 12a, 12b and 12c, respectively, which are openings formed in the insulating layer between the load resistors and underlying cell components so that the load resistors may contact selected cell components. The load resistor contacts V.sub.CC line 10 through load resistor via 12c and contacts interconnects 7a and 7b through load resistor vias 12a and 12b, respectively. In this way, the drain of each pull down transistor of the cell is connected to V.sub.CC line 10 through a load resistor, as is schematically illustrated in FIG. 1.
Solid lines 28a and 28b each outline conductive metal I lines 13a and 13b which run parallel to gates 1 and 2 of the pull down transistors. Metal lines 13a and 13b are insulated from the underlying cell components. Shading type 29 shown in FIG. 4 indicates conductive metal II lines 14a and 14b which run parallel to word line 8 and V.sub.SS line 9. Metal II lines 14a and 14b are positioned above but are insulated from metal I lines 13a and 13b. Together metal I lines 13a, 13b and metal II lines 14a, 14b help complete the circuitry of the SRAM array. Metal I lines 13a and 13b function as bit lines BL and BL. Metal II line 14a functions as a low resistance word line by occasionally contacting word line 8 (contact not shown) to carry that current. Metal II line 14b acts as a global word line for supplying current to other word lines from the word line current source (not shown).
Contacts 16a and 16b connect the drains of the pass transistors and the bit lines. Contacts 16a and 16b are formed by depositing a layer of metal in vias opened in a dielectric layer and over the entire device. Etching the layer of metal in a well known manner produces metal I lines 13a and 13b overlying contacts 16a and 16b which electrically contact conductive portions 11a and 11b, respectively. Because the conductive portions 11a, 11b contact the drains of the pass transistors through buried contacts 15a, 15b, respectively, the electrical connection between the drains of the pass transistors and the bit lines is complete.
The circuit lines and interconnects of the cell, including word line 8, V.sub.SS line 9, V.sub.CC line 10, cross-coupling interconnects 7a and 7b and conductive portions 11a and 11b are conductive layers above the surface of the substrate. Therefore, each circuit line and interconnect consumes semiconductor substrate area.